Beyond the node name: gate-all-around and backside power.

Two changes, two engineering questions

TSMC reports that its N2 nanosheet technology entered volume production in the fourth quarter of 2025. Intel describes its 18A platform through RibbonFET gate-all-around transistors and PowerVia backside power delivery. These are manufacturer-specific platforms, not interchangeable implementations. The public descriptions establish the direction of the technology; they do not establish that two customer chips have identical performance, cost or production maturity.

Gate-all-around improves the gate's electrostatic control around a channel. Backside power changes how supply current reaches devices and how power routing competes with signal routing. A better transistor can still be constrained by supply droop; cleaner power distribution cannot remove every logic or interconnect delay. Their combination is therefore interesting at system level, but each benefit needs its own measurement and an explicitly defined comparison.

Sources: [1] TSMC: N2 technology and production status · [2] Intel: 18A, RibbonFET and PowerVia

Why the node label is insufficient

A process name is a generation identifier, not a complete measurement of every physical feature. It does not reveal the size of an SRAM cell, the pitch of each metal layer, contact resistance or the area of a useful standard cell. Comparing platforms through their names alone replaces a multidimensional engineering decision with an ordering that may not match the actual circuit.

A meaningful design study holds the workload and design objectives constant. It records library options, operating voltage, timing corner, memory organisation, interconnect assumptions and utilisation. Performance should be reported at a stated power budget, or power at a stated performance target. Otherwise an apparent process advantage may partly be a design choice, a different margin or an easier comparison baseline.

A transparent power calculation

The first-order switching-power relation is P_dynamic = alpha C V^2 f, where alpha is activity, C switched capacitance, V voltage and f frequency. In an illustrative comparison with unchanged activity, capacitance and frequency, reducing voltage from 0.8 V to 0.7 V changes dynamic power by (0.7/0.8)^2 = 0.766: a reduction of about 23.4%. This is a calculation under fixed assumptions, not a measured saving from either manufacturer.

Total chip power also includes leakage, memories, interfaces, clocks and other circuits. Lower voltage can reduce timing margin or require a different implementation. A package or server has further power consumers. The calculation is useful because it shows why voltage matters strongly; it becomes misleading when applied directly to the whole system without accounting for the parts that do not follow the same scaling.

Power delivery must be evaluated dynamically

A simple DC approximation, delta V = I R, explains why resistance matters, but workloads do not draw a constant current. A sudden activity change also interacts with inductance, capacitance and regulator response. The relevant question is the supply waveform seen by critical circuits during a demanding transition, not just the nominal rail voltage or a resistance extracted at room temperature.

We would examine droop distributions, thermal gradients, current density and recovery under representative workload changes. This includes interfaces and memory bursts as well as logic stress. The design should retain a clear boundary between laboratory characterisation, sign-off modelling and production measurements, with the same definitions and calibration assumptions carried through the comparison.

Integration changes the qualification plan

Backside connections make wafer handling, bonding, alignment and package interactions part of the device discussion. Imec's connectivity research illustrates why front-to-back integration is an active technical field. A demonstrated structure provides evidence about a specific module; it is not, by itself, proof of high-volume yield across a complete customer design.

Our proposed qualification ladder starts with device and interconnect tests, proceeds through representative circuits and then reaches a packaged workload. At each step, the team should identify which failure modes became observable and which remain untested. Electrical performance and manufacturing reproducibility need separate evidence, because an excellent individual sample can coexist with a difficult process window.

Sources: [3] Imec: front- and backside wafer connectivity

COTT assessment

The strategic change is a shift from transistor-only optimisation to the joint design of devices, power, interconnect and packaging. For a system integrator, the useful output is a reproducible performance envelope rather than a winning process name. It should include operating conditions, failure boundaries and the cost of maintaining margin as workload and temperature change.

We would prioritise application-level measurements and supplier documentation before drawing conclusions about an individual product. Public process announcements are valuable inputs, but cannot substitute for a design-specific acceptance test. This article is our analysis of external technology evidence, not an announcement of a COTT foundry process, a manufacturing agreement or a validated chip.